Conventional sensing circuits exploited in semiconductor memories, particularly non-volatile semiconductor memories having the so-called NOR memory matrix architecture, have the general structure depicted schematically in FIG. 5. The matrix bit line BL that includes a memory cell MC selected for reading is electrically connected to a first circuit branch 501, containing a load P-channel MOSFET P51 connected in a current-mirror configuration to a diode-connected P-channel MOSFET P52 in a second circuit branch 503; the second circuit branch 503 is run through by a reference current IREF, generated by a reference current generator 505.
In series to the load MOSFET P51, i.e., between the load MOSFET P51 and the bit line BL, a cascode-connected N-channel MOSFET N51 is provided, typically of the so-called natural or native type (in jargon, a low threshold voltage MOSFET, having a threshold voltage determined simply by the doping level of the doped semiconductor well within which the MOSFET is formed, without any threshold voltage adjustment dopant implant); the cascode-connected MOSFET N51 is inserted in a negative feedback network comprising an inverter 507 having input and output respectively connected to the source and to the gate of the MOSFET N51.
Typically, the reference current generator 505 is formed by a reference memory cell, structurally identical to the memory cell MC, set in a well-known state and connected to a respective reference bit line. For reasons of symmetry of the two circuit branches 501 and 503, a circuit arrangement including a cascode-connected MOSFET controlled by a feedback-connected inverter similar to that provided in the branch 501 is also provided in the reference circuit branch 503.
Circuit nodes corresponding to the drains of the MOSFETs P51 and P53 are connected to the inverting and non-inverting inputs of a differential amplifier 509, that amplifies a voltage difference between these two circuit nodes.
An equalization N-channel MOSFET N53 acting as a pass transistor (alternatively, a transfer gate) is provided for substantially short-circuiting the two circuit branches 501 and 503 at the drains of the MOSFETs P51 and P53, in a specific phase of a sensing operation.
A sensing operation is made up of two distinct phases: a bit line precharge phase and an evaluation phase.
In the precharge phase, the bit line BL is precharged to a predetermined potential; the equalization MOSFET N53 is turned on (equalization signal EQ asserted high), thereby the first circuit branch 501 is short-circuited to the second circuit branch 503; in this way, during the precharge phase, the potential at the drain of the MOSFET P51 is kept equal to that at the drain of the MOSFET P53.
During the precharge phase, the potential of the word line WL to which the memory cell MC belongs is also raised to a read word line potential, typically the supply voltage VDD of the integrated circuit, or a higher voltage generated by charge pumps.
At the end of the precharge phase, the equalization MOSFET N53 is turned off, and the potential at the drains of the MOSFETs P51 and P53 evolves dynamically; in particular, the evolution in time of the drain potential of the MOSFET P51 depends on the fact that memory cell MC sinks more or less current, and thus on the datum stored in the memory cell. The potentials of the drains of the MOSFETs P51 and P53 are compared to each other by the differential amplifier 509, which amplifies a slight potential difference to a full-swing logic signal. This phase of the sensing operation is the evaluation phase.
It can be appreciated that in the conventional sensing circuit described so far, the inputs of the differential amplifier 509 are connected to circuit nodes (the drains of the MOSFETs P51 and P53) that are decoupled from the relatively heavily loaded nodes corresponding to the respective bit lines (matrix bit line BL and reference bit line) by means of the cascode-connected MOSFETs.
The conventional sensing circuit described schematically in the foregoing is affected by some problems.
One of the problems of the conventional sensing circuit is that, depending of the electrical load offered by the bit line to the load MOSFET P51 and the cascode-connected MOSFET N51, more or less pronounced overshoots in the bit line potential may take place during the precharge. This has a detrimental effect on the sensing operation, because the cascode-connected MOSFET N51 is only capable of delivering current to the bit line, and is not instead capable of sinking current therefrom; thus, if the bit line potential exceeds the target voltage to be reached at the end of the precharge phase, there is nothing (exception made for possible small current leakages) that can (in a reasonably short time) bring the bit line potential back to the target value.
This problem is also encountered when the bit line starting potential before the start of the precharge phase is higher than the target potential. To this purpose, a bit line discharge circuit path is normally provided for, which is activated before the precharge phase so as to discharge the bit line to ground and ensure that the bit line potential starts from a value lower than the target value.
Another problem of the above described circuit is due to the fact that the presence of the cascode-connected MOSFET N51 in series to the bit line BL actually sets a lower limit to the reduction of the supply voltage VDD. In this respect, the use of a natural MOSFET, having a relatively low threshold voltage, is also disadvantageous, because in some technological processes natural MOSFETs are not as good as normal MOSFETs, which have a higher threshold voltage set through a dedicated threshold-voltage adjustment dopant implant.
Additionally, in the evaluation phase, the evaluation of the datum stored in the memory cell MC to be sensed is brought about by a circuit element (the differential amplifier) different from the circuit element (the cascode-connected MOSFET N51) that is used for precharging the bit line. This may introduce errors in the sensing operation, because the two circuit elements are normally affected by different offsets.